1. Field of the Invention
The present invention relates to a multilayer interconnection board. In particular, the present invention relates to a multilayer interconnection board arranged to incorporate, for example, electronic components and to include electronic circuits.
2. Description of the Related Art
Multilayer interconnection boards have been previously used to incorporate electronic components and to include electronic circuits. The multilayer interconnection board includes a plurality of laminated ceramic layers and wiring electrodes disposed on principal surfaces of the ceramic layers. Furthermore, via holes are disposed in the ceramic layers in order to connect the wiring electrodes disposed on the principal surfaces of the ceramic layers. Such a multilayer interconnection board is formed by laminating ceramic green sheets provided with wiring electrode patterns and firing the laminate. In such a multilayer interconnection board, a stress caused by a difference in heat shrinkage between the ceramic layer and the wiring electrode or the via hole may be generated during the firing and, thereby, cracking of the ceramic layer may occur. In particular, frequencies of electronic components have increased and the film thickness of the wiring electrode has been increased in order to reduce an insertion loss in a high-frequency region. However, if the film thickness of the wiring electrode is increased, a difference in shrinkage between the wiring electrode, which is a metal material, and the ceramic during the firing becomes significant. Furthermore, warping or deformation of the multilayer interconnection board may occur after the firing.
A multilayer interconnection board as shown in FIG. 17 has been described. The multilayer interconnection board 1 includes a plurality of laminated ceramic layers 2. A via hole 3 is disposed in the ceramic layers 2. Stress release pads 4 having substantially the same size as that of the via hole 3 are disposed in the vicinity of the via hole 3. The stress release pads 4 are defined by concave portions in the ceramic green sheet and that are filled with an electrically conductive paste. When the stress release pads 4 are provided, a stress caused by a difference in heat shrinkage between the via hole 3 and the ceramic layer 2 is redistributed and cracking and warping of the ceramic layer 2 can be prevented. Furthermore, since the stress release pad 4 does not penetrate the ceramic layer 2, a wiring electrode 5 can be provided as a layer under the portions in which the stress release pads 4 are disposed (see, for example, Japanese Unexamined Patent Application Publication No. 10-65286).
However, when the above-described stress release pads are included in the multilayer interconnection board, the stress release pads 4 having substantially the same size as that of the via hole are used. Therefore, the locations at which the stress release pads can be provided are limited. Furthermore, since the size of the stress release pad is relatively large, when the stress release pads are provided, the locations at which the wiring electrode and the via hole can be arranged are limited, and flexibility of the design is reduced.
Moreover, in order to form the stress release pads, concave portions must be formed in the ceramic green sheet but not to penetrate the ceramic green sheet, and the resulting concave portions must be filled with the electrically conductive paste. Consequently, the production process becomes very complicated. Furthermore, in production of the via hole and the stress release pads, it is necessary that the via hole and the stress release pads are disposed at a distance from each other. Consequently, flexibility of the design is reduced. In addition, since the stress release pads are relatively large, the unnecessary portions of the product are increased so as to increase the size and cost of the multilayer interconnection board.